Silicon Wafer Defects Classification Using Deep Learning Techniques

Abstract

The manufacturing of semiconductor wafers is a complex process that is prone to defects. In this study, we present DefectClassifierX, an automated pattern classification system that uses a convolutional neural network model based on the GoogLeNet architecture and leverages CUDA for faster training and testing speed. We aim to improve defect classification in the semiconductor manufacturing process by accurately classifying single and mixed wafer defect patterns. To validate our approach, we conducted thorough experimentation using the newly introduced dataset called "WM 300K+ wafer map [single and mixed]," which consists of 36 different defect patterns. The experiment results show that the precision, recall, and F1-score for testing our model were all measured at 0.97, indicating excellent performance. Also, the results demonstrate a remarkable level of accuracy, with an average classification accuracy of 99.9% for both single and mixed defect types. Our approach outperforms previous studies in wafer defect pattern classification and has the potential to significantly improve the efficiency and effectiveness of wafer defect analysis in semiconductor manufacturing. Additionally, we utilized hyperparameter tuning with Optuna and implemented a patience stop mechanism for improved convergence. Moreover, we incorporated the AdamW optimizer to further enhance the model's performance. DefectClassifierX is compatible with multiple operating systems, ensuring accessibility for a broader user base. While our results are encouraging, further research is needed to address limitations regarding dataset quality, computational resource requirements, and data augmentation techniques. Additionally, it is important to evaluate the model using real wafer map images for practical applicability assessment.